1. Field of Disclosure
The present invention relates to the design of memory systems and more specifically to read leveling of the memory units designed to receive access requests in a sequential chained topology.
2. Related Art
There are several memory systems in which memory units are designed to receive access (read/write) requests in a sequential chained topology. In such systems, a memory controller typically sends control and address information on a single path, which passes the information to each of the memory units sequentially in the same order as in which the memory units are chained. DDR3 (double data rate three) technology based systems are examples of such memory systems, with DRAMs often being used as memory units, as is well known in the relevant arts.
A read leveling operation is often performed prior to reading data from the memory units. A read leveling operation generally determines the accurate value to be used for a compensation delay when read operations are performed later to retrieve corresponding data elements of interest from a memory unit. The compensation delay generally refers to a delay which would be employed by the memory controller in receiving (looking for) a data unit from a memory unit after sending a read request on the chained path. Such compensation delays need to be employed at least since there are various delays in a read request reaching a memory unit and for the retrieved data unit to reach the memory controller as well.
Read leveling needs to be performed for each of the memory units since the accurate values for corresponding compensation delay are different for different memory units. As an illustration, assuming that the propagation delay equals X time units between each successive pair of memory units, that there are N memory units, and that the first memory unit receives a command at time instance t0, successive memory units would receive the same command at (t0, to+X, t0+2X, . . . t0+(n−1)X). These propagation delays are often referred to as fly-by delays at least in relation to DDR3 technology.
Thus, read leveling operation may need to determine the correct value to be used for a compensation delay while reading data elements for each memory unit to counter the fly-by delays (between the memory units as well as to the first memory unit) and address any other timing/delay parameters as relevant to the corresponding environment.
Several errors may be encountered in the absence of read leveling. For example, in a high speed memory system requiring data portions received from different memory units to be assembled as a word, substantial propagation delays can lead to incorrect data portions (e.g., one data portion received from one memory unit in response to one clock edge and another data portion received in response to a different clock edge) being matched/aligned and provided as a corresponding word. In addition, noise or other incorrect signals may be erroneously interpreted as data.
Once the read leveling is performed with a desired level of accuracy, one or more of such problems can be avoided during read operations.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.